Test Vector Wrapper for LTE-PHY Test Bed

Requirement:

Design, Develop and implement a strategy to load, test & analyze the test vectors to and from the Signal-Chain of an LTE-PHY framework.

• PC/MCH Diagnostic application - To drive the test vectors onto the signal chain [SC]
• Test Vector Player [TVP] - To configure, store, read back the TVP MEMORY SEGMENT and provide the test packets to signal chain over its streaming ports.
• Test Vector Recorder [TVR] - To Configure, Monitor and Log the streaming ports and play back when requested by the MCH.
• Flexibility to configure the TAP points of the SC for Monitoring & Playback.
• PN9 Sequence Generator & Detector for Test pattern Injection & Detection

System Overview:

Test Vectors for UL & DL of signal chain are generated using MATLAB and formatted accordingly for debugging. These Test Vectors are loaded into the on-board DDR2 Memory using an MCH/Host Application over a 32-Bit cluster bus Interface.

Test vector player & Recorder functions along with the UL/DL signal chain modules are implemented in FPGA.

TVP role is to load the Memory Segment with the Test data sent from the MCH application over cluster bus, read the Memory segment and construct packets for Signal Chain over the Avalon Streaming ports.

The test Vector Recorder taps the SC ports configured and stores the diagnostic data into the TVR Memory segment after which, it does a play-back operation to flush the data out to the MCH Logging & plotting application.

Cluster bus Interface:

MCH/Host Application configures, controls and monitors the test vector player and recorder [TVPR] over a 32-Bit Cluster Bus interface.

Avalon interface:

Altera’s proprietary bus standard used. 32-Bit Avalon MM Master and Slave configuration used for connecting the various components using SOPC builder. Avalon Streaming Source & Sink ports implemented.

Test Vector Player & Recorder:

TVP provides option to configure the TVP memory segment size from as little as 4 bytes to 128 MB. It uses the High Speed DDR2 SDRAM Memory controller to write the Test data into the On-Board Memory.

It implements the Address and command decoding functions for status & control. Implements glue logic to construct SC packets of different sizes over Avalon streaming ports. Handles different data widths and uses synchronizers to handle multiple clock domains.

In short, it performs Load-Store-Read back the test data to and from Test vector player memory segment and Constructs the packets for Signal chain UL/DL modules.

User has option to configure the memory usage of TVR for diagnostic data logging and play back functions.

Implementation:

• TVPR Implemented in Altera- Startix II GX device
• Coded using VHDL
• TVP & TVR Configuration using command messaging
• High Speed DDR2 Memory controller to store the test vectors & Diagnostic data into on-board DDR2 Memory.
• Option to configure Packet size.
• Firmware for GX-AMC card in a u-TCA Chassis environment.
• 32-Bit Cluster Bus I/F Logic to communicate with MCH Diagnostic application.
• 1 GB On-Board memory to store test vectors and record the diagnostic data.
• 32-Bit Avalon–Bus Interface

Testing and Validation:

• Test scripts for automation
• Standard Testing practices including Unit testing, Integration & System testing etc
• System testing done on the LTE-PHY test bed hardware.
• Test Application for configuring, loading the test vectors , constellation plots & data analysis

Tools:

Quartus II, Signal Tap Logic Analyzer, Model Sim, Bittware Diagnostic Tool-Diag21K, MATLAB, Visual Studio, MS Office (Documentation), MKS Integrity Client (Version Control).

Our offerings:

• Complete Digital design solutions using FPGAs & CPLDs from Xilinx, Altera, Lattice and Actel.
• Rapid prototyping with IP cores
• SOPC Builder & NIOS Processor Environment
• Verification & Validation
• Test bench Automation Using Scripting [Tcl/Perl]