“Do’s and Don’ts” when considering an FPGA to structured ASIC design methodology

“Do’s and Don’ts” when considering an FPGA to structured ASIC design methodology

More and more engineers are considering structured ASICs when they are designing advanced systems, because these components offer low unit cost, low power, and high performance along with fast turn-around.

In a structured ASIC, the functional resources – such as logic, memory, I/O buffers – are embedded in a pre-engineered and pre-verified base layer. The device is then customized with the top few metal layers, requiring far less engineering effort to create a low cost ASIC (Fig 1). This reduces not only the time and development costs, but also the risk of design errors, since the ASIC vendor only needs to generate metallization layers. With 90-nm process technologies, structured ASICs offer the density and performance required to meet a wide range of advanced applications.

  1. Standard cell ASIC (top) versus structured ASIC (bottom). However, there is still risk involved when it comes to developing a structured ASIC. Errors in the logic design can still exist, so one way to avoid time-consuming and costly silicon re-spins is to use FPGA prototyping and to then convert the design from an FPGA to some form of ASIC. FPGA prototyping is more successful for structured ASICs compared to standard cell ASICs when the structured ASIC mirrors the resources available on the FPGA. The closer the match between the I/O and memory of the FPGA and the structured ASIC, the lower the risk when the design is converted to an ASIC.

Some “Do’s and Don’ts” to take into account when considering a structured ASIC design methodology are as follows:

Do

Establish a design methodology you can use for a wide range of applications. Make sure your design teams are trained on the tools and the FPGA and ASIC architectures to create the best possible design.

Use a software development environment that reduces the risk of design problems, such as functional logic errors. Logic verification and simulation, along with prototyping the design in an FPGA, is a proven method to ensure the design will work in the system.

Prototype your design with an FPGA using the FPGA features that give you the best performance and functionality. Also, generate the prototype with the IP you need for the application, which may require a soft processor, hard multipliers, and memory. In addition, use high-speed LVDS or other I/O to ensure you are building in the signal integrity needed to have a reliable system.

Test your design in-system as much as possible to verify the design works according to requirements. Make sure the system is tested with the FPGA prototype across the entire voltage and temperature range that the system will experience. That will reduce the risk that when the design is converted to an ASIC it will only operate over a limited temperature range and at nominal voltage.

Design the system to use either an FPGA or the structured ASIC. This allows you two major advantages. First, you can go into production with the FPGA and then change to the ASIC once it is available. That provides the advantage of getting to market faster and promotes a market position. Secondly, if there is an unexpected increase in the demand for ASICs and supplies are insufficient, some systems with an FPGA can be manufactured, thus keeping the production lines running. Finally, using the FPGA at the system’s end-of-life will save you from having to order more ASIC devices that are needed to fulfill manufacturing requirements.

An example is the Altera HardCopy II structured ASIC. Generate your prototype with a Stratix’ II FPGA, then go into production with the Stratix II FPGA while the Altera HardCopy Design Center migrates the design to a pin-compatible HardCopy II device. Once the HardCopy II device is approved and production units are available, the system can be produced using the lower cost HardCopy II device. The combination of Altera Stratix II FPGA and HardCopy II structured ASICs also gives you unique manufacturing flexibility, since you can use either in production. For example, you can use the HardCopy device for low cost, but if you have a sudden increase in demand and need more devices immediately, you can use off-the-shelf Stratix II FPGAs as a substitute. You can also go back to using Stratix II FPGAs exclusively if you need to update the design to fix an error or make a change for a specific customer.

Don’t

Use an FPGA to prototype only logic and low-level I/O (such as LVTTL or LVCMOS). That will limit your design to low-end gate arrays that won’t provide the performance edge needed. Too often, only the logic is prototyped in the FPGA, leading to a misconception of how well the design really works in the system. Many designs also require high-speed memory interfaces, and the best design practice is prototyping to ensure the interface performs as required, particularly across voltage and temperature variations.

Choose an ASIC methodology based only on unit cost. That may save some Bill-of-Material costs but make the system uncompetitive. Include factors such as realistic development time and costs along with total engineering effort. In the long run, an FPGA along with a structured ASIC can provide lower development costs and faster development turn-around time.

Consider only standard cell ASIC technology for ASSP designs. Sometimes, structured ASIC or even FPGAs are right for the annual volumes and the need for fast time to market. Choose the structured ASIC before you look at the market needs for the design. Trying to shoehorn a design into a structured ASIC that is too small or feature limited, results in a system that is DOA in the market.

Consider only single-chip solutions. Sometimes the best way to architect a system can be using two devices rather than one large ASIC. Partitioning the design can reduce overall development time and simplify the design process. You can also reduce the risk of having to re-spin a large ASIC design.

Author : Rob Schreck, Aletra Source :www.design-reuse.com

×

Happy to Help!